2007. 11. 14. 15:18
     

02 NDS Hardware Spec And Memory Map

원문 : http://kkamagui.springnote.com/pages/409612

 

들어가기 전에...

 

1. 하드웨어 사양(Hardware Spec)

 

NDS에 대해서 Wikipedia에 검색을 해봤더니 아래와 같은 정보를 얻을 수 있었다(정말 대단하다 wikipedia~~!!).

Technical specifications

  • Mass: 275 grams (9.7 ounces).
  • Physical size: 148.7 x 84.7 x 28.9 mm (5.85 x 3.33 x 1.13 inches).
  • Screens: Two separate 3-inch TFT LCD, resolution of 256 x 192 pixels, dimensions of 62 x 46 mm and 77 mm diagonal, and a dot pitch of 0.24 mm. Note The gap between the screens is approximately 21mm, equivalent to about 92 "hidden" lines. The lowermost display of the Nintendo DS is overlaid with a resistive touch screen, which registers pressure from one point on the screen at a time, averaging multiple points of contact if necessary.
  • CPUs: Two ARM processors, an ARM946E-S main CPU and ARM7TDMI co-processor at clock speeds of 67 MHz and 33 MHz respectively, with 4 MB of main memory which requires 1.65 volts.
  • Card size
    • Data size: Up to 2 gigabit ( = 2048 Mb or 256 MB).
    • Physical size: 33.0 × 35.0 × 3.8 mm
    • Weight: About 4 grams

The system's 3D hardware performs transform and lighting, texture-coordinate transformation, texture mapping, alpha blending, anti-aliasing, cel shading and z-buffering. However, it uses Point (nearest neighbor) texture filtering, leading to some titles having a blocky appearance. The system is theoretically capable of rendering 120,000 triangles per second at 30 frames per second. Unlike most 3D hardware, it has a limit on the number of triangles it can render as part of a single scene; this limit is somewhere in the region of 4000 triangles. The 3D hardware is designed to render to a single screen at a time, so rendering 3D to both screens is difficult and decreases performance significantly.

The system has two 2D engines, one per screen. These are similar to (but more powerful than) the Game Boy Advance's 2D engine.

Games use a proprietary solid state ROM "Game Card" format resembling the memory cards used in other portable electronic devices such as digital cameras. It currently supports cards up to 2 gigabit[15] in size. The cards always have a small amount of flash memory or an EEPROM to save user data, for example progress in a game or high scores. The game cards are 33.0 × 35.0 × 3.8 mm, and weigh around 3.5 grams (1/8 ounces).

The unit has compatibility with Wi-Fi, and a special wireless format created by Nintendo and secured using RSA security signing (used by the wireless drawing and chatting program PictoChat for the DS). Wi-fi is used for accessing the Nintendo Wi-Fi Connection, where users can use the internet or compete with other users playing the same Wi-Fi compatible game.

 

  위 글을 간단히 요약하면 아래와 같다.

  • LCD : TFT-LCD 256 x 192 pixels
  • CPU :  ARM946E-S main CPU 67MHz. ARM7TDMI co-processor 33 MHz
  • RAM : 4Mbyte
  • Graphic : 3D/2D Engine
  • Input : Key and Touch Pad
  • Communication : Wi-Fi

 

 무엇보다 코어가 듀얼이라서 마음에 든다. @0@)/~ 램이 조금 부족한것 같은데... 어쩔 수 없으니... ㅜ_ㅜ

 아래는 전체적인 구성도이다. http://www.dev-scene.com/NDS/Tutorials_Day_2에서 찾아볼 수 있다.

 

Dov_DS_MemoryMap.png

 

2. 메모리맵(Memory Map)

2.1 전체 구성

 http://www.bottledlight.com/ds/index.php/Memory/Layout 와 http://nocash.emubase.de/gbatek.htm#dsmemorymaps를 참고하면 자세한 메모리 맵의 내용을 볼 수 있다.

 NDS Wiki Tech의 내용을 보면 아래와 같다.

ARM9

Name Region base Size Mirrored Width / modes
ITCM 0x00000000* 16 KB no 32 / all
DTCM 0x00800000* 16 KB no 32 / all
Main RAM 0x02000000 4 MB (8 MB) yes 16 / all
Shared RAM 0x03000000 32 KB yes 32 / 16,32
Registers 0x04000000 * * *
Palette RAM 0x05000000 2 KB yes 16 / 16,32
Video RAM 0x06000000 ? ? 16 / 16,32
Sprite RAM 0x07000000 2 KB yes 16 / 16,32
GBA cart ROM 0x08000000 32 MB no 16 / all
GBA cart RAM 0x0A000000 64 KB yes 8 / 8
BIOS (ARM9) 0xFFFF0000 4 KB no unknown / all

 

ARM7

 

Name Region base End Size Mirrored Width / modes
BIOS (ARM7) 0x00000000 0x00003FFF 16 KB no unknown
Main RAM 0x02000000 0x023FFFFF 4 MB (8 MB) yes 16 / all
Shared RAM 0x037F8000 0x037FFFFF 32 KB ? 32 / 16,32
Private RAM 0x03800000 0x0380FFFF 64 KB yes 32 / 16,32
Registers 0x04000000 * * * *
Wifi Control 0x04800000 0x04800FFF * yes** 16
Wifi MAC memory 0x04804000 0x04805FFF 8 KB yes** 16
GBA cart ROM 0x08000000 0x09FFFFFF 32 MB no 16 / all
GBA cart RAM 0x0A000000 0x0A00FFFF 64 KB yes 8 / 8

The ARM7 BIOS is protected via a PC check. The portion below PROTECTION_CR? can be read when PC < PROTECTION_CR?, and the portion beyond it can be read when PC < 0x4000.

 

The Main RAM is always available to both processors, although one has priority over it, and the other will be delayed if both try to access it at the same time.

The 'shared' RAM actually consists of two banks of 16 KB each, and either one only available to a single processor at a time. They can be switched back and forth, to implement a buffer passing scheme for e.g. wireless packets or a sound buffer.

ITCM and DTCM can be relocated using the system control coprocessor CP15

The ARM9 BIOS provides a handful of functions, but does little in the way of system setup. It clears some memory, then waits for the ARM7 bios to signal that system init is complete.

 ITCM과 DTCM 같은 경우는 조금 특별하므로 co-processor 쪽을 봐야 한다(cp15). 좀더 상세한 내용은 아래의 TCM 쪽에서 살펴보자.

 위의 내용 중에 중요한 부분은 메인 메모리 같은 경우 두 프로세스에서 항상 사용 가능하지만 동시에 접근하면 하나가 먼저 작업하고 다른 하나는 지연된다는 것이다.

 또 다른 중요한 부분은 Shared RAM 같은 경우는 두 프로세스 중에 하나만 접근 가능하고 이것을 스위칭을 통해 다른 프로세스에게 넘겨주는 방식으로 동작하는 것이다. 즉 한쪽이 데이터를 체운 후 다른 쪽이 받아서 처리하는 중계 역할인 버퍼로 사용될 수 있다.

 

 Video RAM영역 같은 경우는 자세하게 나와있지 않는데, 이부분은 GBA Tech의 문서를 보면 아래와 같이 잘 나와있다. http://nocash.emubase.de/gbatek.htm#dsmemorymaps에 내용들이다.

 ARM9

00000000h  Instruction TCM (32KB) (not moveable) (mirror-able to 1000000h)
  0xxxx000h  Data TCM        (16KB) (moveable)
  02000000h  Main Memory     (4MB)
  03000000h  Shared WRAM     (0KB, 16KB, or 32KB can be allocated to ARM9)
  04000000h  ARM9-I/O Ports
  05000000h  Standard Palettes (2KB) (Engine A BG/OBJ, Engine B BG/OBJ)
  06000000h  VRAM - Engine A, BG VRAM  (max 512KB)
  06200000h  VRAM - Engine B, BG VRAM  (max 128KB)
  06400000h  VRAM - Engine A, OBJ VRAM (max 256KB)
  06600000h  VRAM - Engine B, OBJ VRAM (max 128KB)
  06800000h  VRAM - "LCDC"-allocated (max 656KB)
  07000000h  OAM (2KB) (Engine A, Engine B)
  08000000h  GBA Slot ROM (max. 32MB)
  0A000000h  GBA Slot RAM (max. 64KB)
  FFFF0000h  ARM9-BIOS (32KB) (only 3K used)
The ARM9 Exception Vectors are located at FFFF0000h. The IRQ handler redirects to [DTCM+3FFCh].

ARM7
00000000h  ARM7-BIOS (16KB)
  02000000h  Main Memory (4MB)
  03000000h  Shared WRAM (0KB, 16KB, or 32KB can be allocated to ARM7)
  03800000h  ARM7-WRAM (64KB)
  04000000h  ARM7-I/O Ports
  04800000h  Wireless Communications Wait State 0
  04808000h  Wireless Communications Wait State 1
  06000000h  VRAM allocated as Work RAM to ARM7 (max. 256K)
  08000000h  GBA Slot ROM (max. 32MB)
  0A000000h  GBA Slot RAM (max. 64KB)
The ARM7 Exception Vectors are located at 00000000h. The IRQ handler redirects to [3FFFFFCh aka 380FFFCh].

Further Memory (not mapped to ARM9/ARM7 bus)
3D Engine Polygon RAM (52KBx2)
  3D Engine Vertex RAM (72KBx2)
  Firmware (256KB) (built-in serial flash memory)
  GBA-BIOS (16KB) (not used in NDS mode)
  NDS Slot ROM (serial 8bit-bus, max. 4GB with default protocol)
  NDS Slot EEPROM (serial 1bit-bus)

Shared-RAM
Even though Shared WRAM begins at 3000000h, programs are commonly using mirrors at 37F8000h (both ARM9 and ARM7). At the ARM7-side, this allows to use 32K Shared WRAM and 64K ARM7-WRAM as a continous 96K RAM block

사실 Video Memory는 A,B,C,D 외에도 E, F, G, H, I가 있다. 자세한 내용은 03 비디오 모드 제어(Video Mode Control)에서 볼 수 있다.

 

  음~ 갑자기 난데없이 WRAM 이란 용어가 나왔다. 역시나 궁금하니 wikipedia에 물었다.

Window RAM (WRAM)

Window RAM or WRAM is an obsolete type of semiconductor computer memory that was designed to replace video RAM (VRAM) in graphics adapters. It was developed by Samsung and also marketed by Micron Technology, but had only a short market life before being superseded by SDRAM and SGRAM.

WRAM has a dual-ported dynamic RAM structure similar to that of VRAM, with one parallel port and one serial port, but has extra features to enable fast block copies and block fills (so-called window operations). It was often clocked at 50 MHz. It has a 32-bit wide host port to enable optimal data transfer in PCI and VESA Local Bus systems. Typically WRAM was 50% faster than VRAM, but with costs 20% lower. It is sometimes erroneously called Windows RAM, because of confusion with the Microsoft Windows operating systems, to which it is unrelated apart from the fact that window operations could boost the performance of windowing systems.

It was used by Matrox on both their MGA Millennium and Millennium II graphics cards.

 비디오 메모리보다는 빠르고 싸다는데... 데이터 메모리 처럼 쓸 수 있나보다. 어쨋든 추가로 활용할 수 있는 메모리가 많다는 것은 좋은 거니깐 그리 알고 넘어가자.

 

 메모리에 대한 추가 정보는 http://neimod.com/dstek/ 에서 찾아볼 수 있다. 중복된 정보 말고 참고할만한 정보를 추리면 아래와 같다.

Memory mirroring

Every memory section, e.g. main memory, shared iwram, io, vram, palette, etc. are mirrored.
For example, Main Memory from 0200:0000-023F:FFFF is mirrored in 0240:0000-027F:FFFF, 0280:0000-02BF:FFFF, etc. until 02FF:FFFF
An other example, Shared IWRAM from 037F:8000-037F:FFFF, is mirrored from 0300:0000 to 037F:7FFF.
This is for each memory section, although it is sometimes difficult to tell where the mirroring starts and stops, ie. IO.

Shared IWRAM

The name shared IWRAM (consists of 2 16kb blocks) can be misleading, as only one CPU has access to it.
However, using WRAMCNT each 16k block can be assigned to a specific CPU.
When processing is done for example, the block can be assigned to the other CPU quickly for processing, without copying it via main memory or the IPC fifo.

Main Memory

Main memory, consisting of one big block of 4MB memory, can be accessed by both CPU's.
However, only one CPU can read/write/execute from it at a time. When both CPUs are trying to read main memory, one will have priority over the other.
See EXMEMCNT for more information.

 Shared RAM 영역은 WRAMCNT 레지스터를 통해 어느 CPU에서 사용가능한지 제어가 가능한 것 같다. 추후 사용해 보도록 하자.

 

2.2 ITCM, DTCM

 TCM에 대한 자세한 내용은 http://nocash.emubase.de/gbatek.htm#dsmemorycontrolcacheandtcm에서 찾아볼 수 있다. TCM은 ARM9에만 연결되어있으며 아래와 같다.

TCM and Cache are controlled by the System Control Coprocessor,
ARM CP15 System Control Coprocessor

The specifications for the NDS9 are:

Tightly Coupled Memory (TCM)

ITCM 32K, base=00000000h (fixed, not move-able)
  DTCM 16K, base=moveable  (default base=27C0000h)
Note: Although ITCM is NOT moveable, the NDS Firmware configures the ITCM size to 32MB, and so, produces ITCM mirrors at 0..1FFFFFFh. Furthermore, the PU can be used to lock/unlock memory in that region. That trick allows to move ITCM anywhere within the lower 32MB of memory.

Cache
Data Cache 4KB, Instruction Cache 8KB
  4-way set associative method
  Cache line 8 words (32 bytes)
  Read-allocate method (ie. writes are not allocating cache lines)
  Round-robin and Pseudo-random replacement algorithms selectable
  Cache Lockdown, Instruction Prefetch, Data Preload
  Data write-through and write-back modes selectable


Protection Unit (PU)
Recommended/default settings are:

 

Region  Name            Address   Size   Cache WBuf Code Data
  -       Background      00000000h 4GB    -     -    -    -
  0       I/O and VRAM    04000000h 64MB   -     -    R/W  R/W
  1       Main Memory     02000000h 4MB    On    On   R/W  R/W
  2       ARM7-dedicated  027C0000h 256KB  -     -    -    -
  3       GBA Slot        08000000h 128MB  -     -    -    R/W
  4       DTCM            027C0000h 16KB   -     -    -    R/W <= devkit ARM에서는 주소를 0x0B000000로 재설정해서 사용
  5       ITCM            01000000h 32KB   -     -    R/W  R/W
  6       BIOS            FFFF0000h 32KB   On    -    R    R
  7       Shared Work     027FF000h 4KB    -     -    -    R/W
위의 내용중에 DTCM영역에 대해서 잠깐 부연 설명을 하자면, 위의 값은 default로 설정되는 값인데 실제로 devkitARM의 crt0.S 파일을 살펴보면 위 영역을 다시 0xB000000 영역으로 재정의해서 사용함을 알 수 있다. 홈브루 파일을 보면서 헷갈리지 말자.
 
Notes: In Nintendos hardware-debugger, Main Memory is expanded to 8MB (for that reason, some addresses are at 27NN000h instead 23NN000h) (some of the extra memory is reserved for the debugger, some can be used for game development). Region 2 and 7 are not understood? GBA Slot should be max 32MB+64KB, rounded up to 64MB, no idea why it is 128MB?
 
DTCM and ITCM do not use Cache and Write-Buffer because TCM is fast. Above settings do not allow to access Shared Memory at 37F8000h? Do not use cache/wbuf for I/O, doing so might suppress writes, and/or might read outdated values.
The main purpose of the Protection Unit is debugging, a major problem with GBA programs have been faulty accesses to memory address 00000000h and up (due to [base+offset] addressing with uninitialized (zero) base values). This problem has been fixed in the NDS, for the ARM9 processor at least, still there are various leaks: For example, the 64MB I/O and VRAM area contains only ca. 660KB valid addresses, and the ARM7 probably doesn't have a Protection Unit at all. Alltogether, the protection is better than in GBA, but it's still pretty crude compared with software debugging tools.
Region address/size are unified (same for code and data), however, cachabilty and access rights are non-unified (and may be separately defined for code and data).

Note: The NDS7 doesn't have any TCM, Cache, or CP15. 

 홈브루를 컴파일 하는 과정을 살펴보면( 00 NDS makefile 및 NDS 파일 생성 과정 분석 ) ITCM 주소가 0x0000 이 아니라 0x1000000에 위치하도록 되어있는 것을 알 수있다.

 위에서 보면 ITCM들은 펌웨어에 의해서 32Mbyte 영역으로 설정되기 때문에 ITCM의 시작 주소를 바꾸는 것은 불가능하지만 mirror를 시켜서 32Mbyte안 쪽에 어디든지 가능하다. 이것을 Protection Unit을 사용해서 ITCM의 위치와 크기를 0x1000000에 있도록 설정해서 ITCM의 위치를 정확히 찝어 주는 것 같다. 상당히 복잡한 구조다. ㅜ_ㅜ

 

3. I/O 포트 맵(Port Map)

 컨트롤러와 연결된 I/O 주소는 http://nocash.emubase.de/gbatek.htm#dsiomaps 에서 찾을 수 있고 아래와 같다.

ARM9 I/O Map
Display Engine A

4000000h  4    2D Engine A - DISPCNT - LCD Control (Read/Write)
  4000004h  2    2D Engine A - DISPSTAT - General LCD Status (Read/Write)
  4000006h  2    2D Engine A - VCOUNT - Vertical Counter (Read only)
  4000008h  50h  2D Engine A (same registers as GBA, some changed bits)
  4000060h  2    DISP3DCNT - ?
  4000064h  4    DISPCAPCNT - Display Capture Control Register (R/W)
  4000068h  4    DISP_MMEM_FIFO - Main Memory Display FIFO (R?/W)
  400006Ch  2    MASTER_BRIGHT - Master Brightness Up/Down
DMA, Timers, and Keypad
40000B0h  30h  DMA Channel 0..3
  40000E0h  10h  DMA FILL Registers for Channel 0..3
  4000100h  10h  Timers 0..3
  4000130h  2    KEYINPUT
  4000132h  2    KEYCNT
IPC/ROM
4000180h  2  IPCSYNC - IPC Synchronize Register (R/W)
  4000184h  2  IPCFIFOCNT - IPC Fifo Control Register (R/W)
  4000188h  4  IPCFIFOSEND - IPC Send Fifo (W)
  40001A0h  2  AUXSPICNT - Gamecard ROM and SPI Control
  40001A2h  2  AUXSPIDATA - Gamecard SPI Bus Data/Strobe
  40001A4h  4  Gamecard bus timing/control
  40001A8h  8  Gamecard bus 8-byte command out
  40001B0h     romcrypt - (not sure if encryption can be accessed by arm9...?)
Memory and IRQ Control
4000204h  2  EXMEMCNT - External Memory Control (R/W)
  4000208h  2  IME - Interrupt Master Enable (R/W)
  4000210h  4  IE  - Interrupt Enable (R/W)
  4000214h  4  IF  - Interrupt Request Flags (R/W)
  4000240h  1  VRAMCNT_A - VRAM-A (128K) Bank Control (W)
  4000241h  1  VRAMCNT_B - VRAM-B (128K) Bank Control (W)
  4000242h  1  VRAMCNT_C - VRAM-C (128K) Bank Control (W)
  4000243h  1  VRAMCNT_D - VRAM-D (128K) Bank Control (W)
  4000244h  1  VRAMCNT_E - VRAM-E (64K) Bank Control (W)
  4000245h  1  VRAMCNT_F - VRAM-F (16K) Bank Control (W)
  4000246h  1  VRAMCNT_G - VRAM-G (16K) Bank Control (W)
  4000247h  1  WRAMCNT   - WRAM Bank Control (W)
  4000248h  1  VRAMCNT_H - VRAM-H (32K) Bank Control (W)
  4000249h  1  VRAMCNT_I - VRAM-I (16K) Bank Control (W)
Maths
4000280h  2  DIVCNT - Division Control (R/W)
  4000290h  8  DIV_NUMER - Division Numerator (R/W)
  4000298h  8  DIV_DENOM - Division Denominator (R/W)
  40002A0h  8  DIV_RESULT - Division Quotient (=Numer/Denom) (R/W?)
  40002A8h  8  DIVREM_RESULT - Division Remainder (=Numer MOD Denom) (R/W?)
  40002B0h  2  SQRTCNT - Square Root Control (R/W)
  40002B4h  4  SQRT_RESULT - Square Root Result (R/W?)
  40002B8h  8  SQRT_PARAM - Square Root Parameter Input (R/W)
  4000300h  4  POSTFLG - Undoc
  4000304h  2  POWCNT1 - Graphics Power Control Register (R/W)
3D Display Engine
4000320h..6A3h
Display Engine B
4001000h  4    2D Engine A - DISPCNT - LCD Control (Read/Write)
  4001008h  50h  2D Engine B (same registers as GBA, some changed bits)
  400106Ch  2    MASTER_BRIGHT - 16bit - Master Brightness Up/Down

4100000h  4    IPCFIFORECV - IPC Receive Fifo (R)
  4100010h  4    Gamecard bus 4-byte data in, for manual or dma read
Hardcoded RAM Addresses for Exception Handling
27FFD9Ch   ..  NDS9 Debug Stacktop / Debug Vector (0=None)
  DTCM+3FF8h 4   NDS9 IRQ Check Bits (hardcoded RAM address)
  DTCM+3FFCh 4   NDS9 IRQ Handler (hardcoded RAM address)
Main Memory Control
27FFFFEh  2    Main Memory Control
Further Memory Control Registers
ARM CP15 System Control Coprocessor

ARM7 I/O Map
4000004h  2   DISPSTAT
  4000006h  2   VCOUNT
  40000B0h  30h DMA Channels 0..3
  4000100h  10h Timers 0..3
  4000120h  4   debug siodata32
  4000128h  4   debug siocnt
  4000130h  2   keyinput
  4000132h  2   keycnt
  4000134h  2   debug rcnt
  4000136h  2   EXTKEYIN
  4000138h  1   RTC Realtime Clock Bus
  4000180h  2   IPCSYNC - IPC Synchronize Register (R/W)
  4000184h  2   IPCFIFOCNT - IPC Fifo Control Register (R/W)
  4000188h  4   IPCFIFOSEND - IPC Send Fifo (W)
  40001A0h  2   AUXSPICNT - Gamecard ROM and SPI Control
  40001A2h  2   AUXSPIDATA - Gamecard SPI Bus Data/Strobe
  40001A4h  4   Gamecard bus timing/control
  40001A8h  8   Gamecard bus 8-byte command out
  40001B0h  4   Gamecard Encryption
  40001B4h  4   Gamecard Encryption
  40001B8h  2   Gamecard Encryption
  40001BAh  2   Gamecard Encryption
  40001C0h  2   SPI bus Control (Firmware, Touchscreen, Powerman)
  40001C2h  2   SPI bus Data
  4000204h  2   EXMEMSTAT - External Memory Status
  4000206h  2   WIFIWAITCNT
  4000208h  4   IME
  4000210h  4   IE
  4000214h  4   IF
  4000240h  1   VRAMSTAT - VRAM-C,D Bank Status (R)
  4000241h  1   WRAMSTAT - WRAM Bank Status (R)
  4000300h  1   POSTFLG
  4000301h  1   HALTCNT (different bits than on GBA) (plus NOP delay)
  4000304h  2   POWCNT2  Sound/Wifi Power Control Register (R/W)
  4000308h  4   BIOSPROT - Bios-data-read-protection address
Sound Registers
4000400h 100h Sound Channel 0..15 (10h bytes each)
  40004x0h  4  SOUNDxCNT - Sound Channel X Control Register (R/W)
  40004x4h  4  SOUNDxSAD - Sound Channel X Data Source Register (W)
  40004x8h  2  SOUNDxTMR - Sound Channel X Timer Register (W)
  40004xAh  2  SOUNDxPNT - Sound Channel X Loopstart Register (W)
  40004xCh  4  SOUNDxLEN - Sound Channel X Length Register (W)
  4000500h  2  SOUNDCNT - Sound Control Register (R/W)
  4000504h  2  SOUNDBIAS - Sound Bias Register (R/W)
  4000508h  1  SNDCAP0CNT - Sound Capture 0 Control Register (R/W)
  4000509h  1  SNDCAP1CNT - Sound Capture 1 Control Register (R/W)
  4000510h  4  SNDCAP0DAD - Sound Capture 0 Destination Address (W?)
  4000514h  2  SNDCAP0LEN - Sound Capture 0 Length (R/W)
  4000518h  4  SNDCAP1DAD - Sound Capture 1 Destination Address (W?)
  400051Ch  2  SNDCAP1LEN - Sound Capture 1 Length (R/W)
gamecart...
4100000h  4   IPCFIFORECV - IPC Receive Fifo (R)
  4100010h  4   Gamecard bus 4-byte data in, for manual or dma read
WLAN Registers
4808036h  2   W
  4808158h  2   W
  480815Ah  2   W
  480815Ch  2   R
  480815Eh  2   R
  4808160h  2   W
  4808168h  2   W
  480817Ch  2   W
  480817Eh  2   W
  4808180h  2   R
  4808184h  2   W
Hardcoded RAM Addresses for Exception Handling
 
380FFDCh  ..  NDS7 Debug Stacktop / Debug Vector (0=None)
  380FFF8h  4   NDS7 IRQ Check Bits (hardcoded RAM address)
  380FFFCh  4   NDS7 IRQ Handler (hardcoded RAM address)

 

 

4. 마치며...

 일단 간단하게 NDS의 메모리 맵에 대해 알아보았다. 시스템 프로그램을 하려면 메모리맵은 필수이므로 자주 참고하도록 하자.

 

 

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Posted by 호기심 많은 kkamagui(까마귀, 한승훈)

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